Frequency and Voltage Scaling Design

Frequency and Voltage Scaling Design

Scaling the supply voltage of CMOS is possible over a technology-specific range; gate delays, setup and hold times, and memory access times scale monotonically with reduced operating voltage over a limited range. Linear voltage reduction results in a square-law reduction in both dynamic and leakage power.

Voltage scaling, when paired with frequency reduction based on workload, can significantly reduce dynamic power consumption. It is effective in older technology nodes like 0.18µm and 0.13µm but less effective in modern nodes like 90nm unless specialized low-leakage processes are used.

However, voltage scaling introduces design and implementation complexities, especially for portable battery-powered devices.

9.1 Dynamic Power and Energy

Dynamic power in CMOS circuits is governed by the equation:

Pdyn=Ceff×Vdd2×fclockP_{dyn} = C_{eff} \times V_{dd}^2 \times f_{clock}

Key points:

• Reducing frequency proportionally reduces power.
• Voltage reduction results in quadratic power savings.
• Energy is the power integrated over time. Lower frequency alone doesn't save energy unless paired with voltage scaling.

Static leakage must be considered when frequency is reduced since tasks take longer, prolonging leakage.

9.2 Voltage Scaling Approaches

Voltage scaling techniques include:

• Static Voltage Scaling (SVS): Fixed voltages per block.
• Multi-level Voltage Scaling (MVS): Switching between discrete levels.
• Dynamic Voltage and Frequency Scaling (DVFS): Adjusting voltage and frequency dynamically.
• Adaptive Voltage Scaling (AVS): Feedback control loop for real-time adjustments.

This chapter focuses on DVFS and AVS.

9.3 Dynamic Voltage and Frequency Scaling (DVFS)

DVFS Operation Steps

1. Increasing Frequency
   • Program the power supply to a higher voltage.
   • Wait for voltage stabilization.
   • Increase clock frequency.
2. Decreasing Frequency
   • Reduce clock frequency.
   • Lower the supply voltage.

Design Challenges

• Determining suitable voltage-frequency pairs.
• Ensuring reliable timing models.
• Managing settling times for power supplies and PLLs.

Temperature Inversion

Deep submicron technologies exhibit non-monotonic delay behavior below a certain voltage threshold (approximately 2 × VT). Voltage scaling must remain above this inversion point.

Switching Times

• Voltage changes (microseconds to milliseconds) are slow due to regulator stabilization requirements.
• Frequency adjustments are faster, especially when changing divider values.

9.4 CPU Subsystem Design Issues

DVFS is commonly applied to CPU subsystems. CPUs and caches are typically partitioned to ensure reliable data retention and interface operation. Two designs are common:

1. Unified Voltage Scaling: CPU and cache share the same voltage rail.
2. Independent Scaling: CPU is scaled independently of the cache, requiring level shifters.

Clock trees must account for delays introduced by level shifters.

9.5 Adaptive Voltage Scaling (AVS)

AVS uses on-chip performance monitors to dynamically adjust supply voltage based on real-time silicon characteristics (process, temperature, and voltage variations). This closed-loop system optimizes power consumption more effectively than open-loop DVFS.

9.6 Level Shifters and Isolation

Multi-voltage designs require level shifters at domain boundaries. Isolation is critical for power gating scenarios. For simplicity, interfaces often use unidirectional level shifting.

9.7 Voltage Scaling Interfaces – Effect on Synchronous Timing

As voltage varies, so do clock tree delays, complicating timing synchronization. Solutions include:

• Asynchronous Interfaces: Simplifies timing but adds latency.
• Latch-Based Retiming: Uses latches to handle skew across clock domains.
• Register-Based Retiming: Aligns CPU and bus clocks to minimize latency.

9.8 Control of Voltage Scaling

Efficient DVFS requires workload-awareness. Policies, like ARM's Intelligent Energy Manager (IEM), analyze task behavior to predict and adjust performance needs dynamically.

The accuracy of DVFS performance control directly affects energy efficiency. Systems must strike a balance between responsiveness and power savings.

References

1. Lasbouygues, B. et al., “Temperature Dependence in Low Power CMOS UDSM Process”, in E. Macii et al. (Eds.) PATMOS 2004, LNCS 3254, 2004.