IP Design for Low Power

 

Chapter Overview

This chapter describes low power design from the perspective of engineers designing complex IP such as processors, DSPs, USB, PCI Express, and bus infrastructure. Unlike previous discussions that assumed a fixed IP structure, here we explore how to design IP to meet low power objectives effectively.

Modern chips predominantly utilize IP, whether from third-party vendors or developed internally. Effective IP design involves accommodating diverse applications, each with potentially unique power strategies. The following techniques are fundamental in designing IP for low power:

• Partitioning for power gating
• Explicit power gating support
• Development of reference power intent files
• Clock and reset strategy design
• IP packaging to support low power
• Verification under varying low power conditions

8.1 Architecture and Partitioning for Power Gating

8.1.1 How and When to Shut Down

Power gating strategies differ based on the IP type. For the SALT chip, we employed distinct approaches for the CPU and USB OTG:

• CPU: Software-controlled power-down sequence with an interrupt mechanism for wake-up.
• USB OTG: Idle-based power-down, contingent on CPU authorization and USB inactivity for 3ms.

8.1.2 What to Shut Down and What to Keep Alive

In the USB OTG core:

• Powered up: Bus Interface Unit, PHY Interface block, Clocks and Reset block.
• Power gated: Protocol engine and Control and Status Registers.

Clock domain synchronization requires non-deterministic request-acknowledge handshakes due to varying domain timings.

8.2 Power Controller Design for the USB OTG

The USB OTG power controller is implemented as a conditional state machine using ifdef directives. It manages the following signals:

Control Signals:

• pwr_reset_n: Protocol engine reset
• gate_hclk: AHB clock control
• h2pd_stop_pclk: PHY clock control
• bius_pwr_clamp: AHB domain output clamp
• h2pl_pwr_clamp: PHY domain output clamp
• pwr_dwn_req_n: Power down request
• retain_n: Retention control

Input Signals:

• pwr_dwn_ack_n: Power down acknowledgment
• stop_pclk_ack: PHY clock stop acknowledgment
• pwr_clamp_ack: Isolation clamp acknowledgment
• suspend_detected: USB bus inactivity detection
• fifo_flushed: FIFO empty indicator
• wkup_res_det: USB bus activity detection
• enable_power_gating: CPU-controlled gating permission

Power Down Sequence:

1. Wait for fifo_flushed.
2. Assert bius_pwr_clamp and h2pl_pwr_clamp.
3. Wait for pwr_clamp_ack.
4. Assert gate_hclk and h2pd_stop_pclk.
5. Wait for stop_pclk_ack.
6. Assert retain_n.
7. Assert reset_n.
8. Assert pwr_dwn_req_n.
9. Wait for pwr_dwn_ack_n.

Power Up Sequence:

1. De-assert pwr_dwn_req_n.
2. Wait for pwr_dwn_ack_n.
3. De-assert reset_n.
4. De-assert retain_n.
5. De-assert gate_hclk and h2pd_stop_pclk.
6. Wait for stop_pclk_ack.
7. De-assert bius_pwr_clamp and h2pl_pwr_clamp.
8. Wait for pwr_clamp_ack.

8.3 Issues in Designing Portable Power Controllers

Portable power controllers must accommodate diverse libraries and possible system-level power controllers. Key considerations:

• Signal polarity: Parameterize polarity for flexible library compatibility.
• Request/Acknowledge handshakes: Implement universally but allow bypass when unnecessary.
• Save/Restore control: Support single-signal or dual-signal configurations.

System-level controllers may be required to sequence power-up events, mitigating simultaneous block activations and potential noise.

8.4 Clocks and Resets

Clock and reset management is critical for:

• Scan testing: Muxing scan clocks and controlling resets.
• Power gating: Clock stoppage and selective reset assertion.

Recommendation: Implement a dedicated clock and reset module for maximum flexibility.

8.5 Verification

Power gating verification follows a two-step process:

1. Functional Testing: Validate core functions with power gating disabled.
2. Power Gating Testing: Re-run tests with gating enabled, simulating power switching at RTL level by forcing register outputs to "X".

Gate-level simulations capture switching fabric characteristics and timing effects.

8.6 Packaging IP for Reuse with Power Intent

Soft IP packaging should include:

• Configurable RTL with test bench generation
• Synthesis scripts supporting power-saving techniques
• Power controller configurability
• Pre- and post-synthesis power operation testing
• Configurable UPF code

8.7 UPF for the USB OTG Core

With UPF, power gating components can be described via TCL commands instead of RTL modifications. Below is an example configuration:

set_scope $otg
create_power_domain otg_power_domain -elements {aiu pfc mac sync csr}
create_supply_net switched_VDD -domain otg_power_domain
set_domain_supply_net otg_power_domain -primary_power_net switched_VDD -primary_ground_net /$top_VSS

create_power_switch power_switch -domain otg_power_domain \
    -input_supply_port {sw_input_port  /$top_VDD} \
    -output_supply_port {sw_output_port  switched_VDD} \
    -control_port {sw_control_port  biu/pwr_dwn_req_n} \
    -ack_port {pwr_ack_port biu/pwr_dwn_ack_n} \
    -on_state {pwr_on_state sw_input_port {sw_control_port ==1}} \
    -off_state {pwr_off_state {sw_control_port ==0}}

set_isolation otg_isolation -domain otg_power_domain -isolation_power_net $top_VDD -clamp_value 0
set_isolation_control otg_isolation -domain otg_power_domain -isolation_signal biu/bius_pwr_clamp

set_retention otg_retention -domain otg_power_domain -retention_power_net $top_VDD
set_retention_control otg_retention -domain otg_power_domain \
    -save_signal {biu/retain_n negedge} -restore_signal {biu/retain_n posedge}

8.8 USB OTG Power Gating Controller State Machine

The controller employs a hierarchical state machine with three primary states:

• TOP_IDLE: Awaits suspend_detected_interrupt.
• SLEEP: Initiates the power-down process.
• WAKEUP: Manages the wake-up sequence.

SLEEP Substates:

1. SLEEP_IDLE: Initial state.
2. CLAMP: Assert clamp signals.
3. CLOCKS_OFF: Disable AHB and PHY clocks.
4. SAVE: Trigger register retention.
5. RESET_PDN: Assert reset signal.
6. PWR_DOWN: Request power down.
7. SLEEP_DONE: Transition back to TOP_IDLE.

WAKEUP Substates:

1. WAKEUP_IDLE: Initial state.
2. PWR_UP: De-assert power down request.
3. RESET_OFF: De-assert reset.
4. RESTORE: Restore retained registers.
5. CLOCKS_ON: Enable clocks.
6. CLAMPS_OFF: Release clamps.
7. WAKEUP_DONE: Return to TOP_IDLE.

RTL Implementation (Excerpt):

always @ (posedge hclk or negedge hreset_n) begin
  if (!hreset_n) begin
    bius_pwr_reset_n <= 1'b1;
    pwr_clamp_n_tmp <= 1'b1;
    main_state <= TOP_IDLE;
    SLEEP_state <= SLEEP_IDLE;
    WAKEUP_state <= WAKEUP_IDLE;
  end else begin
    case (main_state)
      TOP_IDLE: if (suspend_detected_interrupt && enable_power_gating) main_state <= FLUSH_FIFO;
      SLEEP: if (SLEEP_state == SLEEP_DONE && (sp2ht_wkup_res_det_biu || !enable_power_gating)) main_state <= WAKEUP;
      WAKEUP: if (WAKEUP_state == WAKEUP_DONE) main_state <= TOP_IDLE;
      FLUSH_FIFO: if (fifo_flushed) main_state <= SLEEP;
    endcase
  end
end

The USB OTG IP employs these mechanisms to achieve efficient, flexible low power design while ensuring broad applicability across different applications and platforms.