Standard Low Power Methods

Standard Low Power Methods

This document describes various mature techniques used in low-power design.

1. Clock Gating

Clock gating is a technique to reduce dynamic power consumption by disabling clock signals when not needed.

• Clock buffers contribute to up to 50% of dynamic power consumption.
• Automatic clock gating tools detect circuits where gating can be applied without function changes.
• Modern libraries provide specific clock gating cells recognized by synthesis tools.

Results

A study by Pokhrel found that implementing clock gating in a 180nm chip led to:

• Area reduction of 20%
• Power savings of 34%-43%
• Placing clock gating cells early in the clock path saved significant power.

2. Gate Level Power Optimization

Optimization techniques at the gate level reduce dynamic power:

• Restructuring high-activity nets to reduce capacitance.
• Mapping high-activity nets to low-power input pins.
• Cell sizing and buffer insertion optimize timing and power.

3. Multi-VDD

Multi-VDD design assigns different voltage levels to different functional blocks to minimize power consumption.

• Dynamic power is proportional to VDD², so lowering VDD reduces power.
• Cache RAMs run at the highest voltage for speed, while less critical parts run at lower voltages.
• Challenges include power grid complexity and level shifting.

4. Multi-Threshold Logic

Using multiple threshold voltage (VT) transistors reduces leakage current:

• High-VT cells reduce leakage but are slower.
• Low-VT cells are fast but have higher leakage.
• A dual-VT flow optimizes both timing and power.

5. Summary of Low Power Techniques

Technique	Power Benefit	Timing Penalty	Area Penalty	Architecture Impact	Design Impact	Verification Impact	Place & Route Impact
Clock Gating	High	Low	Low	Low	Low	Low	Medium
Gate Level Optimization	Medium	Little	None	None	Low	Low	Low
Multi-VDD	High	Medium	Medium	High	Medium	Low	Medium
Multi-VT	Medium	Little	Low	Low	Low	Low	Low