Clocking Techniques and Clocked Storage Elements for System on a Chip
Abstract
Clocking considerations and clocked storage elements for System on a Chip (SoC) are discussed. Various SoC clocking methods are addressed. We discuss key issues such as "time borrowing" and absorption of clock uncertainties. Clock power-saving techniques suitable for SoC are also described.
I. Introduction
Clocking strategy is one of the most critical design decisions in digital systems. Poor clocking decisions can lead to high costs in system bring-up and diagnostics while reducing the system's reliability over its lifetime. With clock speeds doubling every 2-3 years, clocking considerations are becoming increasingly significant.
As clock frequencies increase, the number of logic levels in the critical path decreases. Modern high-speed processors execute instructions in a single cycle, driven by a single-phase clock. With pipeline stages reaching 15-20, and logic levels per stage decreasing to as low as 10, synchronous design techniques face significant challenges.
In SoC environments, higher clock frequencies pose additional issues, including:
- Inability of signals to cross chip boundaries within a single clock period
- Challenges in distributing the clock signal over large chip areas
- Managing clock uncertainties such as jitter and skew
Optimizing clock skew absorption and using faster Clocked Storage Elements (CSE) can directly enhance performance.
II. Clocking Considerations for SoC
SoC clock subsystems must satisfy diverse requirements, with multiple clock domains operating at different frequencies. Wire delay becomes significant, often exceeding a single clock cycle.
Two key timing parameters affect clock signals:
- Clock Skew: Variations in clock arrival time across different chip locations.
- Clock Jitter: Temporal variations in clock signal transitions.
Clock distribution methods include:
- RC Matched Tree: Uses precisely tuned resistance-capacitance paths to distribute clocks.
- Clock Grid: Provides uniform clock distribution but at higher power consumption.
SoC designs increasingly require adaptive de-skewing mechanisms and a combination of synchronous and asynchronous clocking.
III. Clocked Storage Elements
A. Master-Slave Latch
Uses two latches clocked with non-overlapping phases to avoid transparency issues. The master captures data, and the slave holds it until the next clock phase.
B. Flip-Flop
Unlike latches, flip-flops are edge-sensitive and only capture data at clock transitions, making them more reliable for synchronous designs.
C. Time Window Based Flip-Flops
Uses short pulses instead of full clock edges to define when data is latched, reducing timing uncertainty.
D. Pulsed Latches
Uses local clock pulses to minimize pipeline overhead, though it introduces potential hold-time violations.
IV. Timing Parameters
A. Setup and Hold Time
Setup time requires data to be stable before the clock edge, while hold time ensures data remains stable after the clock edge.
B. Time Borrowing & Clock Uncertainty Absorption
By allowing data to move across clock edges, time borrowing improves logic operation time. Clock uncertainty absorption mitigates jitter and skew.
V. Power Management
Power consumption in SoC designs is given by:
E_switching = Σ (α_0-1(i) * C_i * V_swing * V_DD)
Techniques for reducing power include:
- Reducing active nodes
- Lowering voltage swing
- Technology scaling
- Reducing switching activity
A. Dual Edge Triggering
Utilizes both clock edges to halve clock frequency while maintaining data throughput, reducing power consumption by up to 50%.
B. Dual Edge Triggered Flip-Flop
Uses pulse-generating latches to capture data on both rising and falling edges, improving energy efficiency.
VI. Conclusion
As clock frequencies continue to rise, clocking strategies for SoC must evolve. While current techniques remain viable, wire delay scaling challenges will necessitate new approaches.
Future designs will require a mix of synchronous and asynchronous techniques, particularly as multi-core SoC architectures emerge. The challenge will be to balance performance, power efficiency, and clock distribution complexity.