Physical Standard Libraries

Low Power Design: Standard Cell Libraries and Memory Requirements

12.1 Standard Cell Libraries

12.1.1 Cell Height and Performance

Standard cell libraries are tuned based on performance, power, and area requirements. The cell height, measured in tracks, significantly influences timing and routing characteristics.

• Tall Track Height Libraries (11-12 tracks): Support complex routing and larger drive strength transistors but exhibit higher leakage power.
• Low Track Height Libraries (7-8 tracks): Optimize area efficiency but provide lower drive strength, making them unsuitable for high-speed designs.
• Standard Track Height Libraries (9-10 tracks): Offer a balance between area efficiency and performance and are commonly used in designs.

12.1.2 Threshold Voltage Variants

Libraries can utilize different threshold voltages to optimize for power and performance:

• High-VT Libraries: Lower leakage power but reduced performance; ideal for non-critical paths.
• Low-VT Libraries: High speed but significant leakage power; suited for performance-critical paths.
• Regular-VT Libraries: Provide a middle ground between performance and leakage.

Additional Techniques:

• Use of long channel-length gates to reduce leakage.
• Exploiting the "stack-effect" by using series transistors to minimize leakage.

12.1.3 Modeling of Standard Cell Libraries

Standard cell libraries provide abstract models for efficient design implementation without exposing sensitive circuit details. Essential models include:

• Timing Models: Support multi-corner synthesis and timing analysis.
• Physical Models: Provide layout abstracts with power and signal ports.
• Functional Models: Enable gate-level netlist simulation.
• Power Models: Aid dynamic and leakage power optimization.
• Test Models: Support Automatic Test Pattern Generation (ATPG) and ensure fault coverage.

12.1.4 Characterization of Standard Cell Libraries

Modern semiconductor technology introduces complexities like temperature inversion and voltage scaling:

• Temperature Inversion: At sub-90nm nodes, gate delay decreases with temperature under low VDD due to changes in threshold voltage (VT).
• New Library Timing Models: Traditional resistor-based models are replaced by Composite Current Source (CCS) models to account for multi-voltage and temperature inversion effects.

12.2 Special Cells - Isolation Cells

Isolation cells prevent floating inputs and crowbar currents when power domains are powered down. Isolation can be implemented on either the input or output side.

12.2.1 Signal Isolation Techniques

Three primary isolation methods:

1. Clamp to Logic '0': Implemented using an AND-style isolation cell.
2. Clamp to Logic '1': Achieved with an OR-style isolation cell.
3. State Retention Isolation: Uses a latch to retain the last known state.

Implementation Guidelines:

• Use global always-on signals for control.
• Minimize isolation cell usage by identifying domains that sleep and wake simultaneously.
• Place isolation cells close to domain boundaries.

12.2.2 Output Isolation vs. Input Isolation

• Output Isolation: Requires fewer cells and simplifies control but demands custom cells.
• Input Isolation: Easier to implement with standard cells but requires multiple control signals and cells.

12.2.3 Sneak DC Leakage Paths

Isolation cells may create unintended leakage paths if improperly designed. Preventive measures:

• Avoid pass-gate logic at domain interfaces.
• Analyze interface signals for potential sneak paths.
• Ensure proper pull-up/down transistors to manage floating inputs.

12.3 Special Cells - Level Shifters

Level shifters handle signal transitions across domains with different supply voltages.

12.3.1 Types of Level Shifters

• High-to-Low Shifter: Simple inverter structure; tolerates slight overvoltage within safe limits.
• Low-to-High Shifter: Requires specialized circuitry to drive high-voltage domain inputs.

12.3.2 Layout and Design Considerations

• Separate N-wells for different voltage domains.
• Multiple-cell row heights for well separation.
• Integrated isolation functionality for simplified implementation.

12.4 Memories

Memory components, often generated from compilers, must support multi-voltage and power-gated designs.

12.4.1 Memory Architectures

• Single or multi-ported RAMs.
• Architectures optimized for performance, area, or power.

12.4.2 Memory Interface Design

• Use integrated level shifters and clamps.
• Place interface elements close to the memory to reduce timing complexity.

12.4.3 Retention Techniques

• Retain memory contents during power-down via retention cells.
• Clamp inputs to prevent floating signals.

12.5 Power Gating Strategies and Structures

Power gating reduces leakage by switching off the supply to idle circuitry.

12.5.1 MT-CMOS vs. MV-CMOS

• MT-CMOS: Uses high-VT switches to cut off supply rails.
• MV-CMOS: Employs low-VT switches with overdrive techniques, adding design complexity.

12.5.2 Fine-Grain vs. Coarse-Grain Power Gating

• Fine-Grain: Integrates sleep transistors into each cell.
  • Pros: Simple synthesis, low wake-up latency.
  • Cons: High area overhead, special cell libraries required.
• Coarse-Grain: Utilizes shared switches for entire blocks.
  • Pros: Lower area overhead, flexibility in design.
  • Cons: Complex power network, in-rush current management required.

Recommendation: Coarse-grain gating is generally preferred due to its superior area efficiency.

12.6 Power Gating Cells

Power switches, both header and footer types, manage power delivery in gated domains.

• Footer Switches (NMOS): Provide better conduction efficiency.
• Header Switches (PMOS): Simpler integration with VDD rails.

Design Considerations

• Use parallel transistor arrays for better current handling.
• Implement staged activation to control in-rush current.

12.7 Power-Gated Standard Cell Libraries

Power-gated designs require adjustments to timing models due to IR drop across switches.

• Over-constrain synthesis targets initially.
• Use voltage de-rating models to accurately predict cell delays.

Practical Tips:

• Plan for a 5-10% performance drop in power-gated designs.
• Conduct detailed static and dynamic IR drop analysis.

This comprehensive guide provides an in-depth understanding of standard cell libraries and memory requirements for low-power, multi-voltage, and power-gated designs. Careful selection of libraries, isolation techniques, memory configurations, and gating strategies is crucial for achieving optimal performance with minimal power consumption.