IT

Implementing Multi-Voltage, Power Gated Designs

zeah 2025. 2. 14. 09:41
반응형

Chapter 11: Implementing Multi-Voltage, Power Gated Designs

This chapter describes the implementation of designs that use power gating and multi-voltage techniques. It highlights the areas in the implementation process specific to these techniques, using a multi-voltage power-gated ARM1176JZF-S microprocessor as an example.

ARM1176JZF-S Synthesizable Applications Processor

11.1 Design Partitioning

Partitioning a design into separate power domains introduces new interfaces that may contain isolation cells and level shifters, impacting the overall performance. This task involves system architects, RTL designers, and implementation engineers.

11.1.1 Logical and Physical Hierarchy

  • Assign hierarchical functional units to power domains.
  • Map entire CPU to VCPU, cache to VRAM, and AXI bus to VSOC.
  • Maintain high correlation between power domain and logical hierarchy.

11.1.2 Critical Path Timing

  • Identify and minimize the impact on critical paths, especially between the cache system and CPU logic.
  • Place isolation cells and level shifters carefully.

11.2 Design Flow Overview

The flow for a multi-voltage, power-gated design follows a standard implementation process with exceptions like:

  • Defining power intent.
  • Creating power domains during synthesis.
  • Inserting level shifters, isolation cells, and retention flops.
  • Multi-voltage power network synthesis.
  • Power-aware clock tree synthesis.

11.3 Synthesis

Synthesis maps RTL to target technology while considering power intent.

11.3.1 Power Intent

  • Captured via RTL, HDL pragmas, tool-specific commands, or UPF.

11.3.2 Defining Power Domains and Connectivity

  • Use create_power_domain for domain definition.

11.3.3 Isolation Cell Insertion

  • Insert isolation logic at interfaces of power-gated blocks.

11.3.4 Retention Register Insertion

  • Use set_retention and set_retention_control for state retention.

11.3.5 Level Shifter Insertion

  • Insert level shifters automatically with set_level_shifter.

11.3.6 Scan Synthesis

  • Minimize scan chain crossing of power domains.

11.3.7 Always-On Network Synthesis

  • Use always-on buffers for control signals.

11.4 Multi-Corner Multi-Mode Optimization

Analyze design across multiple modes and corners.

11.5 Design Planning

Determine chip topology and create voltage areas.

11.5.1 Creating Voltage Areas

  • Use guard bands to isolate voltage areas.

11.5.2 Power Gating Topologies

  • Apply grid design for power network.

11.5.3 In-Rush Current Management

  • Daisy-chain switch control to manage in-rush current.

11.5.4 Recommendations

  • Guard-band voltage areas.
  • Place isolation cells and level shifters at boundaries.

11.6 Power Planning

Use automated power network synthesis.

11.6.1 Decoupling Capacitor Insertion

  • Place decaps near switch cells to reduce noise.

11.7 Clock Tree Synthesis

Use bottom-up clustering to minimize skew.

11.8 Power Analysis

Perform static and dynamic IR drop analysis.

11.9 Timing Analysis

Analyze all modes and corners, including OCV considerations.

11.10 Low Power Validation

Validate the implementation through:

  • Gate-level simulation.
  • Equivalence checking.
  • Rule-based methods.

11.11 Manufacturing Test

Address increased power consumption during testing and manage delay variations across operating voltages.

반응형